// Copyright (C) 1953-2022 NUDT
// Verilog module name - packet_digest_generate
// Version: V4.0.20220525
// Created:
//         by - fenglin 
////////////////////////////////////////////////////////////////////////////
// Description:
//         MD generate
///////////////////////////////////////////////////////////////////////////

`timescale 1ns/1ps

module packet_digest_generate #(parameter inport = 6'b000000)
    (
        i_clk,
        i_rst_n,

        iv_addr,                          
        iv_wdata,                                  
        i_wr_pdg,                         
        i_rd_pdg,                         

        o_wr_pdg,          
        ov_addr_pdg,       
        ov_rdata_pdg, 
        
        iv_data,
        i_data_wr,
		iv_pkt_priority,
        iv_eth_type,
  
        i_pkt_bufid_wr,
        iv_pkt_bufid,
        o_pkt_bufid_ack,
        
        ov_pkt,
        o_pkt_wr,
        i_pkt_ack, 
        ov_pkt_bufadd,        

        o_md_wr ,
        ov_md   ,
        i_md_ack, 

        o_pkt_rx_finish,        
        //for discarding pkt while the fifo_used_findows is over the threshold 
        iv_free_bufid_fifo_rdusedw      ,
        iv_rc_police_threshold           ,
        iv_hpriority_be_police_threshold ,
        iv_lpriority_be_police_threshold 

    );

// I/O
// clk & rst
input                   i_clk;
input                   i_rst_n;

input       [18:0]      iv_addr;                         
input       [31:0]      iv_wdata;                              
input                   i_wr_pdg;                        
input                   i_rd_pdg; 
output                  o_wr_pdg;                     
output     [18:0]       ov_addr_pdg;                  
output     [31:0]       ov_rdata_pdg;
//input
input       [8:0]       iv_data;
input                   i_data_wr;
input       [2:0]       iv_pkt_priority;
input       [15:0]      iv_eth_type;

input                   i_pkt_bufid_wr;
input       [8:0]       iv_pkt_bufid;
output                  o_pkt_bufid_ack;

//temp ov_descriptor and ov_pkt for discarding pkt while the fifo_used_findows is over the threshold 
input       [8:0]       iv_free_bufid_fifo_rdusedw       ;
input       [8:0]       iv_rc_police_threshold            ;
input       [8:0]       iv_hpriority_be_police_threshold  ;
input       [8:0]       iv_lpriority_be_police_threshold  ;
//output
output                  o_pkt_wr;       
output      [133:0]     ov_pkt;         
input                   i_pkt_ack;      
output      [15:0]      ov_pkt_bufadd;  

output                  o_md_wr ;
output      [299:0]     ov_md   ;
input                   i_md_ack; 

output                  o_pkt_rx_finish;
//internal wire
wire        [8:0]       data_dee2das;
wire                    data_wr_dee2das;
wire                    md_valid_pde2pds;
wire        [299:0]     md_pde2pds;

wire                    w_pkt_bufid_wr;
wire        [8:0]       wv_pkt_bufid  ;
  
wire                    w_pkt_wr;
wire        [133:0]     wv_pkt  ;
wire        [15:0]      wv_pkt_discard_cnt_pde2cpe;

//wire        [299:0]     wv_md;
//assign ov_md = wv_md[199:0];
packet_digest_extract  #(.inport(inport)) packet_digest_extract_inst(
    .i_clk				(i_clk),
    .i_rst_n			(i_rst_n),
   
    .iv_data			(iv_data),
	.iv_pkt_priority    (iv_pkt_priority),
    .i_data_wr			(i_data_wr),
    .iv_eth_type        (iv_eth_type),
    
    .i_pkt_bufid_wr	  (i_pkt_bufid_wr),
    .iv_pkt_bufid	  (iv_pkt_bufid),    
    
    .iv_free_bufid_fifo_rdusedw		(iv_free_bufid_fifo_rdusedw     ),
    .iv_hpriority_be_police_threshold(iv_hpriority_be_police_threshold),
    .iv_rc_police_threshold			(iv_rc_police_threshold          ),
    .iv_lpriority_be_police_threshold(iv_lpriority_be_police_threshold),

    .ov_data			(data_dee2das),
    .o_data_wr			(data_wr_dee2das),
    .o_pkt_bufid_wr	    (w_pkt_bufid_wr),
    .ov_pkt_bufid	    (wv_pkt_bufid  ),    
    .o_md_wr			(md_valid_pde2pds),
    .ov_md				(md_pde2pds),
    .ov_pkt_discard_cnt (wv_pkt_discard_cnt_pde2cpe)
);  
    
packet_digest_send packet_digest_send_inst(
    .i_clk   		  (i_clk  ),
    .i_rst_n       	  (i_rst_n),
    .i_pkt_bufid_wr	  (i_pkt_bufid_wr),
    .iv_pkt_bufid	  (iv_pkt_bufid),
    .i_md_valid       (md_valid_pde2pds),
    .iv_md       	  (md_pde2pds),             
    .o_pkt_bufid_ack  (o_pkt_bufid_ack), 
    .o_md_wr          (o_md_wr ),
    .ov_md	          (ov_md   ),
    .i_md_ack         (i_md_ack),
    .md_send_state    ()
);

data_splice data_splice_inst(
    .i_clk            (i_clk),
    .i_rst_n          (i_rst_n),
    .i_data_wr        (data_wr_dee2das),
    .iv_data          (data_dee2das),
    .o_pkt_wr         (w_pkt_wr),
    .ov_pkt           (wv_pkt  ),
    .data_splice_state()
); 

input_buffer_interface input_buffer_interface_inst(
    .i_clk          (i_clk),
    .i_rst_n        (i_rst_n),
    .i_pkt_wr       (w_pkt_wr),
    .iv_pkt         (wv_pkt  ),
    .i_pkt_bufid_wr (w_pkt_bufid_wr),
    .iv_pkt_bufid   (wv_pkt_bufid  ),
    .ov_pkt         (ov_pkt       ),
    .o_pkt_wr       (o_pkt_wr     ),
    .ov_pkt_bufadd  (ov_pkt_bufadd),
    .i_pkt_ack      (i_pkt_ack    ),
	.o_pkt_write_finish (o_pkt_rx_finish),
    .input_buf_interface_state()	
);


command_parse_and_encapsulate_pdg command_parse_and_encapsulate_pdg_inst(
    .i_clk                         (i_clk              ),
    .i_rst_n                       (i_rst_n            ),
    
    .iv_pkt_discard_cnt            (wv_pkt_discard_cnt_pde2cpe),
    
    .iv_addr                       (iv_addr            ),                         
    .iv_wdata                      (iv_wdata           ),                        
    .i_wr_pdg                      (i_wr_pdg           ),         
    .i_rd_pdg                      (i_rd_pdg           ),         

    .o_wr_pdg                      (o_wr_pdg           ),         
    .ov_addr_pdg                   (ov_addr_pdg        ),      
    .ov_rdata_pdg                  (ov_rdata_pdg       )
); 
endmodule